Espressif Systems /ESP32-P4 /DMA /CH1_INTSTATUS_ENABLE0

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Interpret as CH1_INTSTATUS_ENABLE0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT)CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT 0 (CH1_ENABLE_DMA_TFR_DONE_INTSTAT)CH1_ENABLE_DMA_TFR_DONE_INTSTAT 0 (CH1_ENABLE_SRC_TRANSCOMP_INTSTAT)CH1_ENABLE_SRC_TRANSCOMP_INTSTAT 0 (CH1_ENABLE_DST_TRANSCOMP_INTSTAT)CH1_ENABLE_DST_TRANSCOMP_INTSTAT 0 (CH1_ENABLE_SRC_DEC_ERR_INTSTAT)CH1_ENABLE_SRC_DEC_ERR_INTSTAT 0 (CH1_ENABLE_DST_DEC_ERR_INTSTAT)CH1_ENABLE_DST_DEC_ERR_INTSTAT 0 (CH1_ENABLE_SRC_SLV_ERR_INTSTAT)CH1_ENABLE_SRC_SLV_ERR_INTSTAT 0 (CH1_ENABLE_DST_SLV_ERR_INTSTAT)CH1_ENABLE_DST_SLV_ERR_INTSTAT 0 (CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT)CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT 0 (CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT)CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT 0 (CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT)CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT 0 (CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT)CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT 0 (CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT)CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT 0 (CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT)CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT 0 (CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT)CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT 0 (CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT)CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT 0 (CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT)CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT 0 (CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT)CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT 0 (CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT)CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT 0 (CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT)CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT 0 (CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT)CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT 0 (CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT)CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT 0 (CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT)CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT 0 (CH1_ENABLE_CH_SUSPENDED_INTSTAT)CH1_ENABLE_CH_SUSPENDED_INTSTAT 0 (CH1_ENABLE_CH_DISABLED_INTSTAT)CH1_ENABLE_CH_DISABLED_INTSTAT 0 (CH1_ENABLE_CH_ABORTED_INTSTAT)CH1_ENABLE_CH_ABORTED_INTSTAT

Description

NA

Fields

CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT

NA

CH1_ENABLE_DMA_TFR_DONE_INTSTAT

NA

CH1_ENABLE_SRC_TRANSCOMP_INTSTAT

NA

CH1_ENABLE_DST_TRANSCOMP_INTSTAT

NA

CH1_ENABLE_SRC_DEC_ERR_INTSTAT

NA

CH1_ENABLE_DST_DEC_ERR_INTSTAT

NA

CH1_ENABLE_SRC_SLV_ERR_INTSTAT

NA

CH1_ENABLE_DST_SLV_ERR_INTSTAT

NA

CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT

NA

CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT

NA

CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT

NA

CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT

NA

CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT

NA

CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT

NA

CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT

NA

CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT

NA

CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT

NA

CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT

NA

CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT

NA

CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT

NA

CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT

NA

CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT

NA

CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT

NA

CH1_ENABLE_CH_SUSPENDED_INTSTAT

NA

CH1_ENABLE_CH_DISABLED_INTSTAT

NA

CH1_ENABLE_CH_ABORTED_INTSTAT

NA

Links

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